HDL IP Collection

The HDL IP Collections stands at the heart of uPlatform, enabling high performance, FPGA based, real time control system implementation. This curated collection of IP blocks, provvided as synthesizable RTL level System verilog allows system designers to build their own virtual System on Chip with minimal effort

CommunicationsControlsSignal chainExternal driversSystem
SPIGPIODownsamplingAD2S1210AXI stream infrastructure
I2CPIDADC CalibrationSI5351Simplebus infrastructure
PWM GeneratorProgrammable faultsfemtoCore processor
abc/dq transformMultichannel enable generation