The HDL IP Collections stands at the heart of uPlatform, enabling high performance, FPGA based, real time control system implementation. This curated collection of IP blocks, provvided as synthesizable RTL level System verilog allows system designers to build their own virtual System on Chip with minimal effort
Communications | Controls | Signal chain | External drivers | System |
SPI | GPIO | Downsampling | AD2S1210 | AXI stream infrastructure |
I2C | PID | ADC Calibration | SI5351 | Simplebus infrastructure |
PWM Generator | Programmable faults | femtoCore processor | ||
abc/dq transform | Multichannel enable generation |